1. Field of the Invention
This disclosure generally relates to techniques for performing mathematical operations within computer systems. More specifically, this disclosure relates to techniques for efficiently performing hardware division in a computer system.
2. Related Art
In order to keep pace with continually increasing microprocessor clock speeds, computational circuitry within the microprocessor core must perform computational operations at increasingly faster rates. One of the most time-consuming computational operations that can be performed within a computer system is a division operation. A division operation involves dividing a dividend, N, by a divisor, D, to produce a resulting approximation of quotient, Q, wherein Q=N/D.
Computer systems often perform division operations using a variant of the SRT technique, which iteratively performs subtraction operations on a remainder, R, to retire a fixed number of quotient bits in each iteration. (The SRT technique is named for Sweeny, Robertson and Tocher, who each independently developed the technique at about the same time.)
Unfortunately, each iteration of the SRT division technique involves performing addition and/or subtraction operations that require time-consuming carry-save additions and selection logic to decide which operations to perform. Hence, hardware implementations of the SRT division technique tend to be relatively slow.
Hence, what is needed is a method and an apparatus for performing a division operation that takes less time than the SRT technique.